export path_filelist=../../testbench/filelist/filelist.f

export vlogan_opts="-full64 -timescale=1ns/1ps -fsdb  -full64    +vc  +v2k  -sverilog  -debug_all "
export vhdlan_opts="-full64 -timescale=1ns/1ps -fsdb  -full64    +vc  +v2k  -sverilog  -debug_all "
export vcs_elab_opts="-full64 -timescale=1ns/1ps -fsdb  -full64  -R  +vc  +v2k  -sverilog  -debug_all -P ${LD_LIBRARY_PATH}/novas.tab  ${LD_LIBRARY_PATH}/pli.a   -debug_pp -t ps -licqueue -l elaborate.log"


export design_libs=xil_defaultlib
export sim_lib_dir=vcs_lib
export lib_dir=${sim_lib_dir}/${design_libs}
export vcs_file=synopsys_sim.setup
export lib_map_path=/home/eda/Xilinx/Vivado/2019.2/vcs_lib

run:clean show setup comp elab sim

show:
	echo "lib_dir ${lib_dir}"

elab:
	@vcs ${vcs_elab_opts} xil_defaultlib.top_tb xil_defaultlib.glbl -o simv	

sim:
	@./simv |tee all_sim.log 

comp:
	@vlogan -work xil_defaultlib ${vlogan_opts} +v2k \
	  -f  ${path_filelist}  \
	  2>&1 | tee -a vlogan.log
	@vlogan -work xil_defaultlib ${vlogan_opts} +v2k \
	    ../../rtl/glbl.v \
	  2>&1 | tee -a vlogan.log	

setup:
	@source ~/.bashrc
	@rm -rf ${vcs_file}
	@touch ${vcs_file}
	@echo "${design_libs}:${sim_lib_dir}/${design_libs}" >> ${vcs_file}
	@echo "OTHERS=${lib_map_path}/synopsys_sim.setup" >> ${vcs_file}
	@rm -rf ${sim_lib_dir}
	@mkdir -p ${lib_dir}	


verdi:
	verdi -f ${path_filelist} -ssf tb.fsdb &


clean:
	@rm -rf ./*.log ${vcs_file} ${lib_dir} csrc simv simv.daidir top_tb_simv.daidir ucli.key ${sim_lib_dir} simulate.do README.txt  novas.conf novas.rc tb.fsdb verdiLog  64
